This invention relates to frequency-multiplying delay-locked loops (DLLs). More particularly, this invention relates to digitally-controlled frequency-multiplying DLLs.
Frequency-multiplying DLLs typically generate a high-frequency clock signal based on a lower frequency reference signal. Such DLLs then attempt to maintain a specific phase relationship between the generated clock signal and that reference signal. A ring oscillator is used to generate an output signal approximately M times the frequency of the reference signal, where the value of M is selectable. Every M pulses of the output signal, the phase of the output signal and the reference signal are compared. The delay of the ring oscillator is then adjusted, if necessary, in response to the comparison. This resets the phase of the output signal with respect to the reference signal. Accordingly, any phase deviation that may occur can accumulate for only M cycles at most before being corrected. Often, the desired phase difference between the generated output signal and the reference signal is zero.
Conventional frequency-multiplying DLLs use analog delay units. The delay of the analog units is adjustable and can be varied by adjusting the supply voltage. These analog delay units are typically controlled by a charge pump and a loop filter. Typically, the output of an odd number of analog inverting delay units connected in series is fed-back to the input of the first unit to form a ring oscillator. The frequency at which the ring oscillator oscillates is dependent on the delay of the analog delay units. By adjusting that delay, the frequency can be varied. However, it is well known that analog designs are more difficult to mass produce within stated specifications and are less portable to various process technologies than digital designs.
In digitally-controlled frequency-multiplying DLLs, the adjustable analog delay units are replaced with digital variable delay lines. To vary the phase of an output signal using a digital variable delay line, the number, not the delay, of the delay units is varied. However, the smallest possible phase increment is typically limited to the delay through a single unit delay, which may not suffice for many applications.
In view of the foregoing, it would be desirable to be able to provide a digitally-controlled frequency-multiplying delay-locked loop.
It would also be desirable to be able to provide a digitally-controlled frequency-multiplying delay-locked loop with fine delay-time adjustment.